1. Field of the Invention
This invention relates to a flip chip packaging process, and more particularly to a packaging process using an underfill as an encapsulant.
2. Brief Description of Related Art
In semiconductor industry, integrated circuit (IC) production includes three stages: wafer production, IC production and IC packaging. Dies are obtained by means of wafer production, circuit design, multiple mask processes and wafer sawing. Each die electrically connects to a carrier via its bonding pads. The carrier can be a packaging substrate or a printed circuit board (PCB). Wires and/or bumps are usually used as intermediate connections between the chip and the carrier. A flip chip interconnection technology may be adapted for fabricating a plurality of bumps in area array on the bonding pads of the chip, and then the chip is flipped over for mounting the chip on the carrier, and the bumps of the chip correspond to the contacts of the carrier. Signals are transmitted via the internal circuit of the carrier and the contacts to an external device such as a motherboard.
As the integration of the chip increases, package structure of the chip becomes diverse. The flip chip package has been applied in the chip packaging field such as chip scale package (CSP), flip chip/ball grid array (FC/BGA) type package due to its advantages of small chip disposing area and short signal transmission path.
FIG. 1A-1C are schematic views of a conventional flip chip packaging process. Referring to FIG. 1A, a substrate 100 is provided. A plurality of chips 110 are mounted on a substrate 100 by flip chip interconnection technology to form a plurality of CSP package units 102. The substrate 100 can be, for example, a multi-layer circuit substrate. An outermost circuit layer of the substrate has a plurality of contacts (not shown). The contacts can be arranged in array or in circle on a chip bonding area (slanted area) of the substrate 100 as an intermediate of electric connection between the substrate 100 and the chip 110.
Referring to FIG. 1B, a plurality of bumps 114 are formed on an active surface of the chip 110 corresponding to the contacts of the substrate for electrical connection between the chip and the substrate. It is noted that in order to reduce damage due to the thermal stress caused by the differential coefficients of thermal expansion between the chip 110 and the substrate 100, an underfill 130 is filled between the chip 110 and the substrate 100 to protect the bumps 114 from being cracked/damaged due to the thermal stress between the chip 110 and the substrate 100.
After the underfill is filled, the chip 110 is exposed from the substrate and thus becomes vulnerable to damage by external forces or get deteriorated by atmospheric dusts or moisture. Therefore, an encapsulant 132 is used to cover the exposed surface of the substrate 100 and the top of the chip 110 in order to protect the chip 110. It is noted that the encapsulant 132 is different from the underfill 130. The encapsulant 132 is subsequently baked at a high temperature to permanently cure. The underfill 130 is formed in a solid state at normal temperature, while it is formed in a semi-solid state when be heated. Therefore, there is a significant difference between the inherent properties of these two materials.
Referring to FIG. 1B, after the chip molding is completed, the substrate 100 and the encapsulant 132 are cut by a sawing machine to form a plurality of flip chip package structures 104, as shown in FIG. 1C. It is noted that in addition to the space between the chips 110 for the sawing tool 10 to cut the substrate 100, a distance D is required for an underfill dispenser to move along edges of the chip as indicated by arrows in FIG. 1A. The distance D is used to prevent the underfill 130 from flooding over a cutting line 112. However, the distance D is limited by the size of the chip in CSP packaging, that is, the area outside the chip bonding area must be less than 20% of total area of all package structures. The limit of the distance D leads to flooding of the underfill 130 over the cutting line 112, which makes dispensing of the underfill difficult and further exposes the interface of the underfill 130 and the encapsulant 132 through the flip chip package structure 104 after the molding and cutting process. Furthermore, since the underfill 130 and the encapsulant 132 are different materials, delamination tends to occur due to the differential coefficients of thermal expansion, and thus the performance of the chip 110 will be deteriorated due to external moisture or temperature change.